Technical Field
The present invention relates generally to semiconductor devices, and more specifically, to a fully-depleted silicon-on-insulator (FDSOI) device for reducing parasitic back gate capacitance.
Description of the Related Art
As the size of metal oxide semiconductor field effect transistors (MOSFETs) and other devices decreases, the dimensions of source/drain regions, channel regions, and gate electrodes of the devices, also decreases. The design of ever-smaller planar transistors with short channel lengths makes it necessary to provide very shallow source/drain junctions. Shallow junctions are needed to avoid lateral diffusion of implanted dopants into the channel, since such diffusion disadvantageously contributes to leakage currents and poor breakdown performance. Shallow source/drain junctions, with a thickness of about 30 nm to 100 nm, are generally required for acceptable performance in short channel devices. Silicon-on-insulator (SOI) technology allows the formation of high-speed, shallow junction devices. In addition, SOI devices improve performance by reducing parasitic junction capacitance.